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?1 cxp83120a/83124a e94843-pk cmos 8-bit single chip microcomputer description the cxp83120a/83124a is a cmos 8-bit single chip microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time base timer, 32khz timer/counter, capture timer counter, lcd controller/driver, remote control reception circuit and 14-bit pwm output besides the basic configurations of 8-bit cpu, rom, ram, and i/o port. the cxp83120a/83124a also provides a sleep/stop function that enables lower power consumption. features wide-range instruction system (213 instructions) to cover various types of data. ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 400ns at 10mhz operation 8s at 500khz 122s at 32khz operation incorporated rom capacity 20kbytes (cxp83120a) 24kbytes (cxp83124a) incorporated ram capacity 644bytes (includes lcd display data area) peripheral functions ?a/d converter 8-bit, 8-channel, successive approximation method (conversion time of 32s/10mhz) ?serial interface 8-bit, 8-stage fifo incorporated (auto transfer for 1 to 8 bytes), 1 channel 8-bit clock synchronized type, 1 channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 16-bit capture timer/counter, 32khz timer/counter ?lcd controller/driver maximum 160 segment display possible (during 1/4 duty) 4 common output, 40 segment output display method static, 1/2, 1/3, 1/4 duty bias method 1/2, 1/3 bias ?remote control reception circuit 8-bit pulse measuring counter, 6-stage fifo ?pwm output circuit 14 bits, 1 channel interruption 15 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp/lqfp piggyback/evaluation chip cxp83200a 100-pin ceramic qfp/lqfp structure silicon gate cmos ic sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin qfp (plastic) 100 pin lqfp (plastic)
?2 cxp83120a/83124a ram 644 bytes clock gen/ system control spc 700 cpu core interrupt controller a/d converter serial interface unit 0 serial interface unit 1 8 bit timer/counter 0 8 bit timer 1 14 bit pwm generator 16 bit capture timer/counter 2 v ss rst xtal1 extal1 v dd nmi/int3 int1 int0 int2 an0 to an7 8 pa0 to pa7 fifo fifo remocon lcd controller/ driver 32khz timer/counter prescaler/ time base timer port a port b port c port d port e port f port g port h 8 8 5 2 8 8 8 8 8 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe4 pf0 to pf7 pg0 to pg7 ph0 to ph7 pe5 to pe6 tex extal2 xtal2 tx av ref av ss seg0 to seg39 vl com0 to com3 vlc1 vlc2 vlc3 pwm rmc cs0 si0 so0 sck0 si1 so1 sck1 ec0 to cint ec1 adj 2 2 2 2 40 4 rom 20k/24k bytes block diagram
?3 cxp83120a/83124a pin assignment (top view) (qfp package) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 80 89 90 10 0 99 98 97 96 95 94 91 92 93 1 pa7/an7 pa1/an1 pa2/an2 pa3/an3 pa4/an4 pa5/an5 pa6/an6 extal1 xtal1 v ss xtal2 av ref av ss v l v lc3 v lc2 v lc1 com0 extal2 pe0/int0/ec0 tex tx pe1/int1/ec1 seg39/pg7 seg38/pg6 seg37/pg5 seg36/pg4 seg35/pg3 v ss nc v dd seg34/pg2 seg32/pg0 seg31/pf7 seg30/pf6 seg29/pf5 seg28/pf4 seg27/pf3 seg33/pg1 seg23/pd7 seg21/pd5 seg20/pd4 seg19/pd3 seg18/pd2 seg17/pd1 seg16/pd0 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 seg22/pd6 seg24/pf0 seg25/pf1 seg26/pf2 com3 com2 com1 pe4/rmc pe6/to/adj pb0/cint pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0 ph1 ph2 ph3 ph4 ph5 pe5/pwm ph6 ph7 pa0/an0 pe3/int3/nmi pe3/int2 rst note) 1. nc (pin 90) is always connected to v dd . 2. v ss (pin 41 and 91) are both connected to gnd.
?4 cxp83120a/83124a pin assignment (top view) (lqfp package) pa7/an7 rst ph6 pa0/an0 pa1/an1 pa2/an2 pa3/an3 pa4/an4 pa5/an5 pa6/an6 extal1 xtal1 v ss xtal2 av ref av ss v l v lc3 v lc2 v lc1 com0 com1 com2 ph7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 81 82 83 84 76 77 78 88 87 86 85 79 80 89 90 10 0 99 98 97 96 95 94 91 92 93 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 seg23/pd7 seg21/pd5 seg20/pd4 seg19/pd3 seg18/pd2 seg17/pd1 seg16/pd0 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com3 seg22/pd6 pe4/rmc pe6/to/adj pb0/cint pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0 ph1 ph2 ph3 ph4 ph5 pe5/pwm extal2 tex tx pe3/int3/nmi pe1/int1/ec1 pe0/int0/ec0 seg39/pg7 seg38/pg6 seg37/pg5 seg36/pg4 seg35/pg3 v ss nc v dd seg34/pg2 seg32/pg0 seg31/pf7 seg30/pf6 seg29/pf5 seg28/pf4 seg27/pf3 seg26/pf2 seg25/pf1 seg24/pf0 pe2/int2 seg33/pg1 note) 1. nc (pin 88) is always connected to v dd . 2. v ss (pin 39 and 89) are both connected to gnd.
?5 cxp83120a/83124a pin description symbol i/o functions i/o/analog input pa0/an0 to pa7/an7 (port a) 8-bit i/o port. i/o can be set in a single bit unit. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) analog inputs to a/d converter. (8 pins) i/o pc0 to pc7 pe0/int0/ ec0 pe1/int1/ ec1 pe2/int2 pe3/int3/ nmi pe4/rmc pe5/pwm pe6/to/ adj ph0 to ph7 input/input/input input/input/input input/input input/input/input input/input output/output output/output/ output i/o (port c) 8-bit i/o port. i/o can be set in a single bit unit. capable of driving 12ma sync current. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (port e) 7-bit port. lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins) (port h) 8-bit i/o port. i/o can be set in a single bit unit. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) external event inputs for timer/counter. (2 pins) external interruption request inputs. (4 pins) non-maskable interruption request input. remote control reception circuit input. 14-bit pwm output. rectangular wave output for 16-bit timer/counter (duty output 50%). output for 32khz oscillation frequency division. i/o/input i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input i/o/output pb0/cint pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 (port b) 8-bit i/o port. i/o can be set in a single bit unit. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) external capture input to 16-bit timer/counter. chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1).
?6 cxp83120a/83124a symbol i/o functions output/output pf0/seg24 to pf7/seg31 (port f) 8-bit output port. (8 pins) output/output pg0/seg32 to pg7/seg39 (port g) 8-bit output port. (8 pins) output/output pd0/seg16 to pd7/seg23 (port d) 8-bit output port. (8 pins) output seg0 to seg15 lcd segment signal output. crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal1; opposite phase clock should be input to xtal1. system clock oscillation of extal1 and xtal1 is used for normal operation mode (max. 10mhz). output com0 to com3 lcd common signal output. v lc1 to v lc3 lcd bias power supply. v l extal1 xtal1 extal2 xtal2 tex tx output input input input output control pin to cut off the current flowing to external lcd bias resistor during standby. crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal2; opposite phase clock should be input to xtal2. system clock oscillation of extal2 and xtal2 is used for sub clock mode (typ. 500khz). crystal connectors for 32khz timer/counter clock generation circuit. connect a 32.768khz crystal oscillator between tex and tx. for usage as event input, connect clock oscillation source to tex, and leave tx open. input input low-level active system reset. nc. under normal operating conditions, connect to v dd . reference voltage input for a/d converter. a/d converter gnd. positive power supply. gnd. two v ss are connected to gnd. rst nc av ref av ss v dd v ss lcd segment signal output.
?7 cxp83120a/83124a ip pull-up resistor port b data port b direction "0" when reset rd (port b) data bus * pull-up transistors approx. 100k w * "0" when reset schmitt input cint cs0 si0 si1 * pull-up transistors approx. 100k w pull-up resistor port b data port b direction "0" when reset rd (port b) data bus ip * "0" when reset schmitt input sck in output enable "0" when reset sck out port b output selection port b 8 pins hi-z hi-z when reset pa0/an0 to pa7/an7 pb0/cint pb1/cs0 pb3/si0 pb6/si1 port b 4 pins 2 pins hi-z pb2/sck0 pb5/sck1 ip pull-up resistor port a data port a direction "0" when reset port a input selection "0" when reset rd (port a) data bus a/d converter * pull-up transistors approx. 100k w * input multiplexer "0" when reset input protection circuit i/o circuit format for pins port a pin circuit format
?8 cxp83120a/83124a 2 pins hi-z hi-z pin when reset circuit format pb4/so0 pb7/so1 pc0 to pc7 8 pins 5 pins hi-z pe0/int0/ec0 pe1/int1/ec1 pe2/int2 pe3/int3/nmi pe4/rmc ip schmitt input int0/ec0 int1/ec1 int2 int3/nmi rmc data bus rd (port e) ip pull-up resistor port c data port c direction "0" when reset rd (port c) data bus * 1 high current drive of 12ma possible * 2 pull-up transistors approx. 100k w * 2 "0" when reset * 1 * pull-up transistors approx. 100k w pull-up resistor port b data port b direction "0" when reset rd (port b) data bus ip * "0" when reset output enable port b output selection "0" when reset so port e port c port b
?9 cxp83120a/83124a 1 pin p in when reset circuit format pe5/pwm port e output selection rd (port e) data bus "0" when reset reset e data "1" when reset pwm port e 1 pin high level pe6/to/adj * 1 * 2 port e data "1" when reset port e output selection mpx port e output selection adj2k adj16k to internal reset signal * 1 pull-up transistors approx. 150k w . adj signals are frequency divider outputs for 32khz oscillation frequency adjustment. adj2k provides usage as buzzer output. * 2 to output enable "00" when reset port e 8 pins hi-z ph0 to ph7 ip pull-up resistor port h data port h direction "0" when reset rd (port h) data bus * pull-up transistors approx. 100k w * "0" when reset port h high level (high level with 150k resistor when reset)
?10 cxp83120a/83124a 24 pins segment output (v dd level) pin when reset circuit format pd0 to pd7 pf0 to pf7 pg0 to pg7 segment data segment driver port/segment output selection "0" when reset port data pd7 to pd4 pd3 to pd0 pf7 to pf0 pg7 to pg0 by a single bit unit by 4-bit unit by 8-bit unit 16 pins seg0 to seg15 v ch v cl 4 pins v dd level com0 to com3 v lc1 v lc2 v lc3 v dd 1 pin hi-z v l lcd control (dsp bit) "0" when reset v dd level port d port f port g segment common
?11 cxp83120a/83124a 2 pins oscillation pin when reset circuit format extal1 xtal1 2 pins extal2 hi-z xtal2 high level extal2 xtal2 2 pins oscillation tex tx 1 pin low level rst extal1 xtal1 ip ip extal2 xtal2 ip ip tex tx ip ip ip op schmitt input mask option pull-up resistor diagram shows circuit composition during oscillation. feedback resistor is removed during stop. xtal1 becomes "high" level. diagram shows circuit composition during oscillation. feedback resistor is removed during stop. xtal2 becomes "high" level. diagram shows circuit composition during oscillation. when the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed and tex and tx become "low" level and "high" level respectively.
?12 cxp83120a/83124a * 1 v in and v out must not exceed v dd + 0.3v. * 2 the high current drive transistor is the n-ch transistor of port c (pc) note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. lcd bias voltage input voltage output voltage high level output current high level total output current low level total output current operating temperature storage temperature allowable power dissipation v dd av ss v lc1 , v lc2 , v lc3 v in v out i oh i oh i ol i olc i ol topr tstg p d low level output current supply voltage ?.3 to +7.0 ?.3 to +0.3 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ? ?0 15 20 100 ?0 to +75 ?5 to +150 600 380 v v v v v ma ma ma ma ma ? ? mw output per pin total for all output pins value per pin, excluding high current outputs value per pin * 2 for high current outputs total for all output pins qfp package lqfp package item symbol rating unit remarks absolute maximum ratings (vss = 0v)
?13 cxp83120a/83124a lcd bias voltage high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v ? v item symbol min. max. unit remarks 4.5 3.5 3.0 2.7 2.5 vss 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 v lc1 v lc2 v lc3 v ih v ihs v ihex v il v ils v ilex topr high-speed mode guaranteed operation range * 1 low-speed mode guaranteed operation range * 1 guaranteed operation range during extal2 clock (sub clock mode) guaranteed operation range with tex clock guaranteed data hold range during stop lcd power supply range * 5 * 2 hysteresis input * 3 extal * 4 * 2 hysteresis input * 3 extal * 4 v dd * 1 during extal1 clock (main clock mode), high-speed mode is 1/2 frequency division clock selection; low- speed mode is 1/16 frequency division clock selection. * 2 value for each pin of normal input ports (pa, pb4, pb7, pc and ph). * 3 value of the following pins; rst, cint cs0, si0, si1, sck0, sck1, ec0/int0, ec1/int1, int2, nmi/int3, and rmc. * 4 specifies only during external clock input. * 5 optimal values are determined by lcd used. recommended operating conditions (vss = 0v)
?14 cxp83120a/83124a v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v v dd = 4.5v, v ih = 4.0v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5v, v lc1 = 3.75v v lc2 = 2.5v v lc3 = 1.25 high level output voltage i/o leakage current supply current * 4 4.0 3.5 0.5 ?.5 0.3 ?.3 0.1 ?.1 ?.5 ?.33 v v v v v ? ? ? ? ? ? ? ? ? ? k k pc pa, pb, pc, pd * 1 , pe5, pe6 pf to pg * 1 v l (only v ol ) extal1 extal2 tex rst * 2 item symbol pins conditions min. pa to pc * 3 , ph * 3 pe0 to pe4, rst * 2 v dd i iz common output impedance r com segment output impedance r seg com0 to com3 seg0 to seg15 seg16 to seg39 * 1 i dd1 high-speed mode operation (1/2 frequency division clock) i dd3 i dds1 i dds3 i ddss v oh v ol i ihe1 i ile1 i ihe2 i ile2 i iht i ilt i ilr i ih i il low level output voltage input current 3 5 typ. 0.4 0.6 1.5 40 ?0 30 ?0 10 ?0 ?00 ?0 ?0 5 15 max. unit i dd2 dc characteristics electrical characteristics (ta = ?0 to +75?, vss = 0v) v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3.5v, 500khz crystal oscillation (c 1 = c 2 = 22pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) sleep mode stop mode v dd = 5.5v, 10mhz, 500khz crystal oscillation and termination of 32khz oscillation v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) 18 40 ma 35 100 a 0.8 2 ma 1.1 8 ma 930a i dds2 v dd = 3.5v, 500khz crystal oscillation (c 1 = c 2 = 22pf) 400 800 a 10 a
?15 cxp83120a/83124a * 1 common pins of pd0/seg16 to pd7/seg23, pf0/seg24 to pf7/seg31, pg0/seg32 to pg7/seg39, pd, pf and pg is the case when the common pin is selected as port; seg16 to seg39 is when the common pin is selected as segment output. * 2 rst specifies the input current when pull-up resitor has been selected; leakage current when no resistor has been selected. * 3 pins pa to pc, and ph specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. (pe0 to pe4 specifies the leakage current.) * 4 when all output pins are left open. clock 1mhz 0v for all pins excluding measured pins input capacity 10 20 pf pins other than pb7, pe5, pe6 v lc1 to v lc3 com0 to com3 seg0 to seg15 pd0/seg16 to pd7/seg23 pf0/seg24 to pf7/seg31 pg0/seg32 to pg7/seg39 av ref , av ss , v dd , v ss item symbol pins conditions min. c in typ. max. unit
?16 cxp83120a/83124a * t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (address: 00fe h ). t sys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11"). extal1 extal2 t xh t xl t cf t cr 0.4v v dd ?0.4v 1/fc aaaa a aa a aaaa aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 aaaa a aa a aaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall time system clock frequency system clock input pulse width system clock input rise and fall time event count input clock pulse width event count input clock rise and fall time system clock frequency event count input clock input pulse width event count input clock rise and fall time f c t xl , t xh t cr , t cf f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal1 extal1 extal1 extal1 xtal2 extal2 extal2 extal2 ec0 ec1 ec0 ec1 tex tx tex tex mhz ns ns mhz ns ns ns ms khz ? ms item symbol pin conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive v dd = 3.0 to 5.5v fig. 1, fig. 2 v dd = 3.0 to 5.5v fig. 1, fig. 2 external clock drive v dd = 3.0 to 5.5v fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 1 37.5 0.3 450 t sys + 50 * 10 typ. 0.5 32.768 max. 10 200 0.7 200 20 20 (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v) fig. 2. clock applied conditions fig. 1. clock timing
?17 cxp83120a/83124a chip select transfer mode (sck0 = output mode) chip select transfer mode (sck0 = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (address: 00fe h ). t sys ( ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") note 2) the load condition for the sck0 output mode, so0 output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v) item cs0 ? sck0 delay time cs0 - ? sck0 float delay time cs0 ? so0 delay time cs0 - ? so0 float delay time cs0 high level width sck0 cycle time sck0 high and low level widths si0 input setup time (for sck0 - ) si0 input hold time (for sck0 - ) sck0 ? so0 delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 input mode output mode input mode output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?50 100 200 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns t sys + 200 100 max. unit conditions tex ec0 ec1 t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr fig. 3. event count clock timing
?18 cxp83120a/83124a fig. 4. serial transfer ch0 timing cs0 sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0
?19 cxp83120a/83124a serial transfer (ch1) (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v) item sck1 cycle time t kcy sck1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 1000 16000/fc 400 8000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns sck1 si1 si1 so1 t kh t kl t sik t ksi t kso sck1 high and low level widths si1 input setup time (for sck1 - ) si1 input hold time (for sck1 - ) sck1 ? so1 delay time symbol pin conditions min. max. unit note) the load condition for the sck1 output mode, so1 output delay time is 50pf + 1ttl. fig. 5. serial transfer ch1 timing 0.2v dd 0.8v dd t kl t kh so1 t kcy t sik t ksi 0.2v dd 0.8v dd t kso 0.2v dd 0.8v dd output data input data si1 sck1
?20 cxp83120a/83124a conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian v zt * 1 v ft * 2 av ref an0 to an7 ta = 25? v dd = av ref = 5.0v v ss = av ss = 0v operation mode sleep mode stop mode 32khz operation mode linearity error zero transition voltage full-scale transition voltage resolution av ref current av ref ? ? v v v dd av ref 1.0 ma 10 a 0.6 160/f adc * 3 12/f adc * 3 v dd ?0.5 0 item symbol pin conditions min. typ. max. unit bits (3) a/d converter characteristics (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = av ss = 0v) 8 ? lsb 70 mv 5030 10 4970 ?0 4910 mv fig. 6. definition of a/d converter terms analog input linearity error v ft v zt 00 h 01 h fe h ff h digital conversion value * 1 v zt : value at which the digital conversion value changes from 00 h to 01 h and vice versa. * 2 v ft : value at which the digital conversion value changes from fe h to ff h and vice versa. * 3 f adc indicates the below values due to the bit 6 (cks) of a/d control register (address: 00f9 h )and the bit 7 (pck1) and bit 6 (pck0) of clock control register (address: 00ff h ). 00 ( f = f ex /2) 01 ( f = f ex /4) 11 ( f = f ex /16) f adc = f c /2 f adc = f c /4 f adc = f c /16 0 ( f /2 selection) cks pck1, pck0 f adc = f c f adc = f c /2 f adc = f c /8 1 ( f selection) i ref i refs
?21 cxp83120a/83124a external interruption high and low level widths reset input low level width int0 int1 int2 nmi/int3 rst 1 32/fc ? ? item symbol pin conditions min. max. unit t ih t il t rsl (4) interruption, reset input (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v) 0.2v dd 0.8v dd t ih t il int0 int1 int2 nmi / int3 (nmi specifies only for the falling edge) t il t ih fig. 7. interruption input timing t rsl 0.2v dd rst fig. 8. rst input timing
?22 cxp83120a/83124a appendix fig. 9. spc700 series recommended oscillation circuit c 1 aaaa a aa a aaaa extal xtal c 2 rd aaaa a aa a aaaa extal xtal (i) main clock 500khz sub clock aaaa a aa a aaaa extal xtal c 1 c 2 rd xtal (ii) main clock 500khz sub clock aaaaa a aaa a aaaaa extal xtal c 1 c 2 rd aaaaa a aaa a aaaaa tex tx (iii) 32khz sub clock manufacturer murata mfg co., ltd. river eletec co., ltd. kinseki ltd. model csa4.19mg csa8.00mg csa10.0mt cst4.19mgw * cst8.00mtw * cst10.00mtw * hc-49/u03 hc-49/u (-s) fc (mhz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 18 30 15 22 30 15 22 560 470 0 2.2k 0 18 c 1 (pf) c 2 (pf) rd ( ) circuit example (i) (ii) (i) those marked with an asterisk ( * ) signify types with built-in ground capacitance (c 1 , c 2 ). item content reset pin pull-up resistor non-existent existent mask option table
?23 cxp83120a/83124a 0 15 10 5 51015 20 (100a) 3 45 6 0.1 5.0 1.0 7 2 0.05 (50a) 0.01 (10a) 0.5 10.0 20.0 v dd ?supply voltage [ v ] i dd vs. v dd (fc = 10mhz main clock, ta = 25?, typical) fc = 500khz sub clock 1/2 frequency dividing mode 32khz sleep mode fc ?system clock [mhz] i dd ?supply current [ma] i dd vs. fc (v dd = 5v, ta = 25?, typical) 1/2 frequency dividing mode main clock 1/2 frequency dividing mode main clock sleep mode i dd ?supply current [ma] fc = 10mhz main clock sleep mode fc = 500khz sub clock sleep mode 32khz mode (instruction) characteristics curves
?24 cxp83120a/83124a sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy package structure 23.9 0.4 qfp-100p-l01 detail a m 100pin qfp (plastic) 20.0 ?0.1 + 0.4 0?to 15 0.15 ?0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 ?0.01 + 0.4 2.75 ?0.15 + 0.35 a 0.65 0.12 0.15 0.8 0.2 (16.3) * qfp100-p-1420-a 1.4g sony code eiaj code jedec code package material lead treatment lead material package weight epoxy/phenol resin solder plating 42 alloy package structure detail a lqfp-100p-l01 * qfp100-p-1414-a 100pin lqfp (plastic) 16.0 0.2 * 14.0 0.1 75 51 50 26 25 1 76 0.5 0.08 0.18 ?0.03 + 0.08 (0.22) a 1.5 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.5 0.2 (15.0) 0?to 10 0.1 0.1 0.5 0.2 100 0.1 note: dimension * ?does not include mold protrusion. package outline unit: mm

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